Xilinx, Inc. Senior Design Verification Engineer - FPGA SoC (Contract) in Singapore

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense

  • Automotive

  • Broadcast

  • Consumer

  • High Performance Computing

  • Industrial / Scientific / Medical (ISM)

  • Wired

  • Wireless

Responsibilities will include:

  • Develop test plans and coverage metrics from specifications, write block and chip-level tests, and execute the test plans from start to finish
  • Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
  • Develop and improve existing verification regression environments

The successful candidate should possess the following qualifications:

  • BSc w/ 6+ years or MSc w/ 4+ years or PhD w/ 2+ years in Electrical Engineering, Computer Engineering, or Computer Science
  • Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip SOCs and FPGAs
  • Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
  • Strong understanding of different phases of ASIC and/or full custom chip development is required
  • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus
  • Verification Experience in protocols like AXI, DDR4, HBM, PCIe, Processors, Graphics is a plus
  • Experience in block level NOC(Net work on Chip) verification is a plus
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan) is a plus
  • Experience in modeling SYSTEMC and using SYSTEMC based models in verification is a plus
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
  • Experience with FPGA programming and software is a plus